How 64MB of Cache Eliminates the Need for 64GB of RAM in Video Servers
Why AMD EPYC 9135 Requires Less RAM Than Intel Xeon Silver 4516Y+ for Video Surveillance
CPU Specifications Comparison
AMD EPYC 9135 (Zen 5 Architecture)
- 16 cores / 32 threads
- 64MB L3 cache (shared)
- 16MB L2 cache total (1MB per core)
- 80KB L1 cache per core
- Chiplet-based architecture
- 12 memory channels
- 200W TDP
Intel Xeon Silver 4516Y+ (Emerald Rapids)
- 24 cores / 48 threads
- 45MB L3 cache (shared)
- ~48MB L2 cache total (2MB per core)
- 64KB L1 cache per core
- Monolithic die architecture
- 8 memory channels
- 185W TDP
How AMD’s Chiplet Architecture Reduces RAM Requirements
1. Superior Cache Hierarchy Per Core
- AMD provides 4MB of cache per core (64MB L3 ÷ 16 cores) versus Intel’s 1.9MB per core (45MB ÷ 24 cores)
- AMD’s larger L3 cache per core keeps more active video frame data on-chip, reducing trips to main memory
- The 80KB L1 cache (vs Intel’s 64KB) means frequently accessed video stream metadata stays closer to the cores
2. Chiplet Architecture Enables Better Data Locality
- AMD’s chiplet design groups cores into Core Complex Dies (CCDs) with dedicated cache pools
- Video streams can be “pinned” to specific chiplets, keeping all processing data within that chiplet’s local cache hierarchy
- This reduces cross-die communication and keeps working data sets in fast on-die cache rather than system RAM
3. Unified L3 Cache Design
- Each AMD chiplet has a unified 64MB L3 cache shared among its cores
- For video surveillance, multiple camera streams processed on the same chiplet can share decoded frame buffers in L3 cache
- Intel’s distributed cache architecture requires more frequent RAM access when cores share video processing workloads
4. More Efficient Memory Channel Utilization
- AMD’s 12 memory channels vs Intel’s 8 means 50% more memory bandwidth
- When cache hits occur (which happens more often due to larger cache), the extra bandwidth isn’t needed
- When RAM access is required, AMD can fetch data faster, reducing the need to “buffer” in RAM
Real-World Impact for Video Surveillance
Cache-Friendly Video Workload Characteristics:
- Frame Buffering: Recent video frames stay in L3 cache for motion detection without RAM roundtrips
- Analytics Working Sets: AI analytics processing on video often reuses the same frame data multiple times—AMD’s larger cache keeps this data on-chip
- Stream Metadata: Camera IDs, timestamps, encoding parameters fit entirely in AMD’s expanded cache hierarchy
Memory Requirement Example:
- A typical 4MP (2688×1520) H.265 stream at 15 FPS requires ~3-4MB of working memory for decoding, buffering, and real-time analytics
- AMD EPYC 9135: With 64MB L3 cache, up to 16-20 concurrent streams can have their active working sets (decoded frames, motion vectors, reference frames) entirely in cache
- Intel Xeon 4516Y+: With 45MB L3 cache spread across 24 cores (~1.9MB per core), only 10-12 streams can be cache-resident before forcing frequent RAM access
Result: AMD systems can process the same number of 4MP surveillance streams with 30-40% less installed RAMbecause video frame data, motion detection buffers, and analytics working sets remain in the processor’s much larger per-core cache pools. Intel systems need additional system RAM to compensate for smaller cache capacity and higher cache-miss rates during multi-stream processing.
Additional Architectural Benefits
5. NUMA Optimization
- AMD’s chiplet design naturally creates NUMA domains that can be optimized for specific camera groups
- Video streams from building sectors can be assigned to specific chiplets, maximizing cache reuse
6. Lower Memory Access Latency
- When cache hits, AMD’s access latency is just ~4 nanoseconds (local L3)
- RAM access is ~100+ nanoseconds—avoiding RAM = 25x faster data access
This architectural advantage makes AMD EPYC particularly well-suited for high-density video surveillance servers where minimizing system cost (through reduced RAM requirements) while maintaining high performance is critical.
